1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming elastically relaxed silicon-germanium (SiGe) virtual substrates on bulk silicon.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Transistors come in a variety of different physical configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. Irrespective of their physical configuration, all FET devices include a doped source region, a doped drain region and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the channel region of the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
Historically, silicon has been the dominant semiconductor material that has been used in fabricated integrated circuit devices. That is, the source region, drain region and the channel region were all formed in silicon. To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, with the constant demand for ever increasing performance relative to previous device generations, device designers are currently investigating using semiconductor materials other than silicon as the basic substrate material, such as silicon germanium (SiGe), germanium (Ge) and so-called III-V materials. Materials such as SiGe and Ge are interesting to devices designers since they exhibit higher carrier mobility (for both electrons (NMOS devices) and holes (PMOS devices) as compared to silicon.
However, the formation of SiGe and Ge materials on silicon can be difficult due to lattice mismatches between such materials (for example there is 4.2% lattice mismatch between silicon and germanium). Due to this lattice mismatch, defects will be generated in a layer of SiGe (with a relatively larger lattice) when it is formed (by epitaxial deposition) on a silicon substrate (relatively smaller lattice) since the SiGe lattice will “shrink” to match the lattice structure of the silicon substrate. Ideally, given required performance demands, a semiconductor material that will be used for the channel region of an advanced transistor device should have, at most, a very limited number of defects (e.g., well below about 10E4 defects/cm2 near the very uppermost surface). One technique that has been employed to try to reduce the number defects in SiGe layers grown on silicon substrates is depicted in FIG. 1A, wherein multiple layers of SiGe (with different concentrations of germanium) with different lattice sizes were formed between the substrate 12 and the final upper layer 18 in an attempt to reduce the number of defects in the uppermost layer 18. More specifically, in one example, a SiGe0.25 layer 14 would be formed on the silicon substrate 12, a SiGe0.60 layer 16 would be formed on the SiGe0.25 layer 14, and finally a layer of substantially pure germanium 18 would be formed on the SiGe0.60 layer 16. The lattice size of the layers 12, 14, 16 and 18 are each greater than the preceding layer or substrate 12. However, by formation of these “graded” layers of SiGe (with varying concentrations of germanium) and varying lattice sizes, it was intended that many of the defects in the lower layers (e.g., 14, 16) would not propagate into the final layer 18, which would serve as the channel semiconductor material. This process involved the plastic relaxation of the SiGe materials due to the fact that defects were generated or created in the layers of SiGe material, especially the lower layers. The graded arrangement of SiGe layers was an attempt to reduce the number of defects at the surface of the uppermost layer, e.g., the layer 18. Inducing such defects sometimes included techniques like exceeding the critical thickness of the material, implanting materials such as helium, hydrogen or argon at the interface between the SiGe layer 14 and the silicon substrate 12, etc. Although the generation of such defects usually served the purpose of achieving relaxation of the films, subsequent processing operations that were performed to reduce the number of defects present in such relaxed films has not been equally successful. As noted above, to the inventor's knowledge, there is no technique that provides for the formation of SiGe films on bulk silicon substrates wherein the defect density in the resulting SiGe film is consistently and reliably at or below about 10E4 defects/cm2.
In contrast to plastic relaxation, elastic relaxation is another technique that is employed in an attempt to form relaxed semiconductor material on compliant substrates. Elastic relaxation of epi material (e.g., SiGe) formed on free-standing silicon beams has been demonstrated on silicon-on-insulator (SOI) substrates where removal of portions of the buried oxide layer (BOX) resulted in “beams” of silicon (the active layer) that were supported by the remaining portions of the buried oxide layer. See, e.g., Liang et al., “Critical thickness enhancement of epitaxial SiGe film grown on small structures,” Journal of Applied Physics, 97, 043519 (2005) and Mooney et al., “Elastic strain relaxation of free-standing SiGe/Si structures,” Applied Physics Letters, 84, 1093 (2004). FIGS. 1B-1E simplistically depict an illustrative process flow for forming such layers on a starting SOI substrate 20. As shown in FIG. 1B, in general, the SOI substrate 20 is comprised of a bulk silicon substrate 22, a buried insulation layer (or “BOX” layer) 24 (that is typically comprised of silicon dioxide), and an active layer 26 comprised of silicon. Transistor devices are normally formed in and above the active layer 26. FIG. 1C depicts the SOI substrate 20 after the active layer 26 has been patterned using known photolithography and etching techniques to expose portions of the BOX layer 24. FIG. 1D depicts the SOI substrate 20 after an isotropic etching process was performed to remove portions of the BOX layer 24 selectively relative to the surrounding materials. This results in the formation of a BOX pedestal 24A that supports the active layer 26. The active layer 26 now constitutes two free-standing beams 26A, 26B of silicon materials that are anchored to the BOX pedestal 24A. FIG. 1E depicts the SOI substrate after a layer of SiGe material 28 was epitaxially grown on the exposed portions of the active layer 26 and on the exposed surface of the substrate 22. The above papers indicate that the SiGe material 28 that is formed on the free-standing beams 26A, 26B of silicon material is elastically relaxed even in cases where the thickness of the SiGe material exceeds its critical thickness because the strain is transferred from the relatively thicker SiGe material 28 to the relatively thinner material—the free-standing beams 26A, 26B—due to the compliant nature of the free-standing beams 26A, 26B relative to the SiGe material 28. In contrast, the SiGe material 28 that is formed on the exposed substrate 22 is in a strained condition because the lattice of the SiGe material 28 “shrinks” to match the smaller lattice of the silicon substrate 22. This occurs because the silicon substrate 22 is much thicker and much stiffer than the SiGe material 28 that is formed on the substrate 22.
However, SOI substrates are significantly more expensive than bulk silicon substrates. Given the competitive nature of the semiconductor manufacturing business, the use of more expensive SOI substrates in manufacturing integrated circuit products would likely make the resulting products too expensive, at least in some applications. What is needed is a technique for manufacturing elastically relaxed SiGe virtual substrates on bulk silicon substrates that is also compatible with existing manufacturing process flows.
The present disclosure is directed to various methods that may solve or reduce one or more of the problems identified above.